1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device with an increased effective channel length and a method of manufacturing the same.
2. Description of the Related Art
The integration density of semiconductor devices continues to increase. The dimensions of devices have decreased to such an extent that at the present time, design rules in the neighborhood of 0.1 μm are possible.
When design rules are decreased, the line width and the channel length of gate electrodes of MOS transistors are scaled down. As a result, short channel effects (SCEs) can occur in the transistors.
The SCEs, result in threshold voltage being lowered and drain current being increased in the MOS transistors affected by channel length modulation. Furthermore there can be velocity saturation, drain induced boundary lowering (DIBL), and the likes.
If threshold voltage is lowered due to the SCEs, DRAM devices suffer degradation in their dynamic refresh characteristics. If ions for modulating threshold voltage are heavily doped to solve this problem, static refresh characteristics are degraded. Such problems are described in detail in the publication by Hamamoto, in “On the Retention Time Distribution of Dynamic Random Access Memory (1998, IEEE, Vol. 45, pp1300-1309).”
To solve SCEs, there are several known techniques for increasing the effective channel length and the line width of gate electrodes. An example of such techniques is disclosed in Korean Patent Application No. 2001-0015244. The technique described in the above referenced patent application results in the formation of a groove in the bottom of the gate electrode.
FIG. 1 relates to the technique described in the above referenced Patent application. With this technique a nitride pattern 12 is formed on a semiconductor substrate 10 where an isolation layer (not shown) is formed, so as to expose a channel formation region of a MOS transistor. Here, the channel formation region of the MOS transistor, i.e., a gate electrode formation region, has a line width of about 0.1 μm, and two portions of the nitride pattern 12 are spaced apart by about 0.1 μm. Insulating spacers 14 are formed on both sidewalls of the nitride pattern 12. The exposed semiconductor substrate 10 is oxidized by local thermal oxidation to form a thermal oxide layer 16.
As shown in FIG. 1B, the thermal oxide layer 16 and the insulating spacers 14 are removed by a wet etch process, thereby forming a recess 18 in the semiconductor substrate 10. Next, a gate insulating layer 22 is formed on the resultant structure of the semiconductor substrate 10 to a predetermined thickness, and a polysilicon layer is deposited on the gate insulating layer 22 so as to sufficiently fill the recess 18. The polysilicon layer 24 is removed using chemical mechanical polishing (CMP) until the nitride pattern 12 is exposed, thereby forming a gate electrode 24.
Referring to FIG. 1C, the nitride pattern 12 on both sides of the gate electrode 24 is removed, and low-concentration impurity ions are implanted into the exposed semiconductor substrate 10, thereby forming a lightly doped region (or an LDD region) 26. Thereafter, sidewall spacers 28 are formed on the both sidewalls of the gate electrode 24 by a known method, and high-concentration impurity ions are implanted into the both sidewall spacers 28, thereby forming a heavily doped region 30. Since the bottom of the gate electrode 24 is formed to be convex due to the recess 18, the channel length can be compensated.
However, the above described method of manufacturing a gate electrode of a MOS transistor requires a number of complicated processes, such as the formation of the nitride pattern 12, the formation of the spacers 14, the formation and removal of the thermal oxide layer 16, the filling of the gate electrode 24, and the like.
Also, the thermal oxide layer 16 obtained by the local thermal oxidation may get stressed due to the adjacent nitride pattern 12. Further, since a bird's beak may occur at both edges of the thermal oxide layer 16, forming the recess 18 in the desired shape is very difficult.